Hybrid Prototyping for Manycore Design and Validation

Leonard Masing, Fabian Lesniak, Jürgen Becker

The trend towards more parallelism in information process- ing is unbroken. Manycore architectures provide both massive parallelism and flexibility, yet they raise the level of complexity in design and pro- gramming. Prototyping of such architectures helps in handling this com- plexity by evaluating the design space and discovering design errors. Several system simulators exist but they can only be used for early soft- ware development and interface specification. FPGA-based prototypes on the other hand are restricted by available FPGA resources or expen- sive multi-FPGA prototyping platforms. We present a hybrid prototyp- ing approach for manycore systems that consists of an FPGA-part and a virtual part of the architecture on a host system. The hybrid proto- typing requires less FPGA resources while retaining its speed advantage and enabling flexible modeling in the virtual platform. We describe the concept, provide an analysis of timing accuracy and syn- chronization of the FPGA with the Virtual Platform (VP) and show an example in which the hybrid prototype is used for feature development and evaluation of a scientific manycore architecture. The hybrid proto- type allows us to evaluate a 7x7 architecture on a Virtex-7 XC7VX485T FPGA board which otherwise could only fit a reduced 2x2 design of our architecture.

Evaluation of FPGA Partitioning Schemes for Time and Space Sharing of Heterogeneous Tasks

Umar Ibrahim Minhas, Roger Woods, Georgios Karakonstantis

Whilst FPGAs have been integrated in cloud ecosystems, strict constraints for mapping hardware to spatially diverse distribution of heterogeneous resources at run-time, makes their utilization for shared multi tasking challenging. This work aims at analyzing the effects of such constraints on the achievable compute density, i.e the efficiency in uti- lization of available compute resources. A hypothesis is proposed and uses static off-line partitioning and mapping of heterogeneous tasks to improve space sharing on FPGA. The hypothetical approach allows the FPGA resource to be treated as a service from higher level and supports multi-task processing, without the need for low level infrastructure sup- port. To evaluate the effects of existing constraints on our hypothesis, we implement a relatively comprehensive suite of ten real high perfor- mance computing tasks and produce multiple bitstreams per task for fair evaluation of the various schemes. We then evaluate and compare our proposed partitioning scheme to previous work in terms of achieved system throughput. The simulated results for large queues of mixed in- tensity (compute and memory) tasks show that the proposed approach can provide higher than 3× system speedup. The execution on the Nal- latech 385 FPGA card for selected cases suggest that our approach can provide on average 2.9× and 2.3× higher system throughput for compute and mixed intensity tasks while 0.2× lower for memory intensive tasks.