UltraSynth: Integration of a CGRA into a Control Engineering Environment

Dennis Wolf, Tajas Ruschke, Christian Hochberger, Andreas Engel, Andreas Koch

Coarse Grained Reconfigurable Arrays (CGRAs) can exploit parallelism of compute-intense applications by distributing their work- load across a set of Processing Elements (PEs). They are highly efficient in computation and flexible due to their reconfigurability. While these attributes make CGRAs highly interesting as general purpose hardware accelerators, their incorporation into a complete computing system raises severe challenges at the hardware and software level. To overcome the stage of a simulated concept, CGRAs need to be applied to the real- world in order to demonstrate the practicability of the overall system. This paper presents the integration of a CGRA into a control engineering environment targeting a Xilinx Zynq System on Chip (SoC). It focuses on the fully automated tool-chain mapping abstract engineering models to CGRA configurations, and on the SoC-internal runtime communication on hardware level.

Exploiting reconfigurable vector processing for energy-efficient computation in 3D-stacked memories

Joao Paulo C. de Lima, Paulo C. Santos, Rafael F. de Moura, Marco A.Z. Alves, Antonio C.S. Beck, Luigi Carro

Although Processing-in-Memory (PIM) architectures have helped to reduce the effect of the memory wall, the logic placed inside 3D-memories still faces the large disparity between DRAM and CMOS logic operations. Thereby, for a broad range of emerging data-intensive applications, the Functional Units (FUs) are usually underutilized, espe- cially when the application presents poor temporal-locality. As applica- tions demand irregular processing requirements on the different parts of their execution, this behavior can be used to reconfigure energy-reduction techniques, either by scaling frequency or by power-gating functional units. In this paper, we present the application-dependable characteris- tics that enable dynamic usage of energy-reduction techniques without performance degradation for highly constrained PIM designs. The exper- imental results show that the exploration of a reconfiguration mechanism can improve PIM system energy efficiency by 5 × and also can effectively benefit both memory-intensive and compute-intensive applications.

Automatic Toolflow for VCGRA Generation to Enable CGRA Evaluation for Arithmetic Algorithms

André Werner, Florian Fricke, Keyvan Shahin, Florian Werner, Michael Hübner

The work, presented in this paper has been carried out within an EU-funded project with the name EXTRA, aimed at creating an envi- ronment to generate, configure and evaluate user-customizable Coarse- Grained Reconfigurable Array (CGRA) architectures, called VCGRA. The tools provide a fully automatic development and evaluation plat- form for a VCGRA architecture including synthesis and execution of the VCGRA with its corresponding hardware configuration and the required interfaces on an FPGA platform. Furthermore, it also provides the nec- essary software modules for data transmission between the processing system (PS) and the VCGRA on reconfigurable hardware. In this paper, the part of the ”VCGRA Toolflow” which is responsible to provide the generation of the VCGRA hardware’s FPGA-bitstream from a specifi- cation is discussed. Especially the generation of the VCGRA hardware, the automatic creation of the required interfaces and the evaluation of the improvements are presented. The toolflow is planned to be an open source project, providing hardware developers with a framework to create extensions for the VCGRA architecture, and to make them accessible for software developers. Many aspects of the hardware can be customized, including the functions provided by the Processing Elements and the communication infrastructure as well as the target platform integration. Furthermore, software developers from the EDA domain are enabled to provide, integrate and evaluate algorithms for application mapping.