Fault-Tolerant Architecture for On-Board Dual-Core Synthetic-Aperture Radar Imaging

Helena Cruz, Rui Policarpo Duarte, Horácio Neto

In this research work, an on-board dual-core embedded architecture was developed for SAR imaging systems, implementing a reduced-precision redundancy fault-tolerance mechanism. This architecture protects the execution of the BackProjection Algorithm, capable of generating acceptable SAR images in embedded systems subjected to errors from the space environment. The proposed solution was implemented on a Xilinx SoC device with a dual-core processor. The present work was able to produced images with less 0.65dB on average, than the fault-free image, at the expense of a time overhead up to 33%, when in the presence of error rates similar to the ones measured in space environment. Notwithstanding, the BackProjection algorithm executed up to 1.58 times faster than its single-core version without any fault-tolerance mechanisms.

Optimizing CNN-based Hyperspectral Image Classification on FPGAs

Shuanglong Liu, Ringo S.W. Chu, Xiwei Wang, Wayne Luk

Hyperspectral image (HSI) classification has been widely adopted in remote sensing imagery analysis applications which require high classification accuracy and real-time processing speed. Convolu- tional neural networks (CNNs) -based methods have been proven to achieve state-of-the-art accuracy in classifying HSIs. However, CNN mod- els are often too computationally intensive to achieve real-time response due to the high dimensional nature of HSI, compared to traditional meth- ods such as Support Vector Machines (SVMs). Besides, previous CNN models used in HSI are not specially designed for efficient implementa- tion on embedded devices such as FPGAs. This paper proposes a novel CNN-based algorithm for HSI classification which takes into account hardware efficiency and thus is more hardware friendly compared to prior CNN models. An optimized and customized architecture which maps the proposed algorithm on FPGA is then proposed to support real-time on- board classification with low power consumption. Implementation results show that our proposed accelerator on a Xilinx Zynq 706 FPGA board achieves more than 70× faster than an Intel 8-core Xeon CPU and 3× faster than an NVIDIA GeForce 1080 GPU. Compared to previous SVM- based FPGA accelerators, we achieve comparable processing speed but provide a much higher classification accuracy.

Supporting Columnar In-Memory Formats on FPGA: The Hardware Design of Fletcher for Apache Arrow

Johan Peltenburg, Jeroen van Straten, Matthijs Brobbel, H. Peter Hofstee, Zaid Al-Ars

As a columnar in-memory format, Apache Arrow has seen increased interest from the data analytics community. Fletcher is a frame- work that generates hardware interfaces based on this format, to be used in FPGA accelerators. This allows efficient integration of FPGA accel- erators with various high-level software languages, while providing an easy-to-use hardware interface for the FPGA developer. The abstract descriptions of data sets stored in the Arrow format, that form the input of the interface generation step, can be complex. To generate efficient in- terfaces from it is challenging. In this paper, we introduce the hardware components of Fletcher that help solve this challenge. These components allow FPGA developers to express access to complex Arrow data records through row indices of tabular data sets, rather than through byte ad- dresses. The data records are delivered as streams of the same abstract types as found in the data set, rather than as memory bus words. The generated interfaces allow for full system bandwidth to be utilized and have a low area profile. All components are open sourced and available for other researchers and developers to use in their projects.