A Novel Encoder for TDCs

Günther Knittel

We present a novel encoder design for FPGA-based Time-to- Digital Converters (TDCs) that use tapped delay lines. The encoder is the most challenging and problematic unit on such measurement devices. Recent developments in TDC methodology include the Wave Union prin- ciple, and encoders based on population count. These two methods can alleviate fundamental disadvantages of FPGA-based TDCs. However, it appeared to be problematic to combine the two methods. The contribu- tion of this paper is a special arithmetic unit that allows us to combine these two methods into a fast and compact encoder. The paper is a report on work in progress, real-world measurement re- sults cannot be given at this point in time.

A Resource Reduced Application-Specific FPGA Switch

Quian Zhao, Yoshimasa Ohnishi, Iida Masahiro, Takaichi Yoshida

Public cloud providers are employing more and more FP- GAs as hardware accelerators in data centers. For large applications that requiring cooperation among multiple FPGAs, a network for connect- ing these accelerators is necessary. Most high-performance commercial switches are designed for general purpose networks, so that have high costs. On the other hand, FPGA-based programmable switches can be customized with minimum necessary functions, but the high-performance full-crossbar design requires too many resources to implement a many- port switch on them. In this work, based on the fact that network topolo- gies of a specific type of applications commonly follow a particular pat- tern, we show a method of designing and implementing an application- specific switch with reduced resources on FPGAs. Our case studies show that such resource reduced switches can implement a high-performance network with low-cost commercial FPGAs.

Software-Defined FPGA Accelerator Design for Mobile Deep Learning Applications

Panagiotis G. Mousouliotis, Loukas P. Petrou

Convolutional neural networks (CNNs) have been success- fully used to attack problems such as object recognition, object detec- tion, semantic segmentation, and scene understanding. The rapid de- velopment of deep learning goes hand by hand with the adaptation of GPUs for accelerating its processes, such as network training and infer- ence. Even though FPGA design exists long before the use of GPUs for accelerating computations and despite the fact that high-level synthesis (HLS) tools are getting more attractive, the adaptation of FPGAs for deep learning research and application development is poor due to the requirement of hardware design related expertise. This work presents a workflow for deep learning mobile application acceleration on small low- cost low-power FPGA devices using HLS tools. This workflow eases the design of an improved version of the SqueezeJet accelerator used for the speedup of mobile-friendly low-parameter ImageNet class CNNs, such as the SqueezeNet v1.1 and the ZynqNet. Additionally, the workflow in- cludes the development of an HLS-driven analytical model which is used for performance estimation of the accelerator.